FPGA development with Vivado design suite to design Xilinx FPGA FROM ZERO using VHDL or VERILOG language!
Platform: Udemy
Status: Available
Duration: 8 Hours
Price: $19.99 $0.00
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What you'll learn
- How to develop Xilinx FPGAs Using Vivado Xilinx tool.
- 30 plus lectures of well-structured, step by step content.
- How to start a project from Zero from opening a new project until the final product for uploading the FPGA with your project.
- Zynq 7000, explained and implementation.
- Connecting Axi Bus to Zynq7000 peripherals and between IPs.
- How to create Bit or Mcs file, and even uploading it to a development board!
- How to open SDK project.
- Axi-Bus, Streamed and Memory-mapped IP's and differences.
- Test Bench, what is it and how to write it.
- How to simulate Vivado projects, using the Modelsim tool or Vivado.
- How to setup the PCIe root complex write a full communication to the Pcie end point and how to simulate the PCIe.
- Adding Xilinx IP to your project.
- Adding ILA ,integrated logic analyzer, the strongest tool for real-time debug.
- Having a PC with windows/Linux and internet connection.
- Basic VHDL/Verilog Knowledge.
- No previous FPGA developing's tool skills are needed.
As it's easy for you to understand, working as an FPGA developer is the most profitable job in the Hardware development industry. And by now, it is a profession with great demand in every big company: Apple, Microsoft, Intel, Amazon, Google and many others!
If you want to work as an FPGA developer or just to know how to design an FPGA this is the course for you!
This Course is in English and has subtitles to 16 different languages!
This Course was made for all levels by a professional electronic and computer engineer. with a huge experience with FPGAs of all of the companies in the market. In this Course we will learn how to use Xilinx FPGAs tool - Vivado design suite.
Students saying:
Paul Burciu: "I appreciate the course as a good one, giving me valuable information about how to program an FPGA board using Vivado and providing such a complex application regarding FPGA implementation of PCI Express. I am thanking the author for his great work on this course."
Amos TangUpdated: "Ofer is a great and active coach."
In this course you will learn everything you need to know for using Vivado design suite. Vivado design suite is a tool that was crated by Xilinx and is used to design Xilinx FPGAs, simulating them and real-time debugging them and of course to program them.
This course was created for beginners who never used Vivado before, and also for students who wants more experience with the Vivado design suite, also this course can help even advanced users for knowing and understanding how to use and design more complex parts in this tool - like Pcie, Axi interface, Simulations with 3rd party tool(Modelsim,Questasim…), Zynq7000 processor and much more.
This course will help the Students understand everything they needs to know for working in big companies with Vivado design suite as a professional designers.
In this course the students will learn how to simulate their project with Vivado and also with 3rd party tool - Modelsim. Students with no experience at Modelsim will learn briefly about Modelsim but i can guarantee that after the Full Project part in the course you will control the Modelsim which is a really easy tool to learn.
At the end of the course it includes a Full Project of 2.5 hours, with PCIE communication and simulating the PCIE Cores. This way after you have learned all of the parts of how to start your own project, you can also go and build a big project by using all of the aspects learned on this course.
The course will start with installing Vivado tool and Modelsim. The next of the course I will create a project and explain step by step, after that in the last 2 lectures I will create the second complex project of PCIe and explain everything.
We cover a wide variety of topics, including:
How to download and install Vivado design suite 2019.1
How to download and install Modelsim
Create new project
Adding block design
Adding Xilinx IP cores
Xilinx Primitive Cores
Xilinx language templates
synthesize a project
Implementing the design
Creating Constraints
Generate Bitstream , Binstream and MCS files
Simulating the design through Vivado or Modelsim
Zynq 7000
Axi interfaces
Open SDK project
Real Time Integration with ILA - logic analyser
PCIE FULL Project with PCIE and Simulating the PCIE.
and much more!
You will get lifetime access to over 30 lectures!
This course comes with a 30 day money back guarantee! If you are not satisfied in any way, you'll get your money back.
So what are you waiting for? Learn FPGA Development in a way that will advance your career and increase your knowledge, all in a fun and practical way!
Who this course is for:
- Anyone who wants to start using Vivado in their career & get paid for their user experience design skills.
- Beginners who have never designed an FPGA before.
- Intermediate FPGA's developers who want to level up their skills!
